UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 147

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
25.1
Other power-saving options
The PSD module offers other reduced power saving options that are independent of the
Power-down mode. Except for the PSD Chip Select Input (CSI, PD2) features, they are
enabled by setting bits in PMMR0 and PMMR2.
Figure 68. Enable Power-down flowchart
Table 102. Power-down mode’s effect on ports
PLD power management
The power and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in PMMR0. By
setting the bit to '1,' the Turbo mode is off and the PLDs consume the specified Standby
current when the inputs are not switching for an extended time of 70 ns. The propagation
delay time is increased by 10 ns (for a 5 V device) after the Turbo Bit is set to '1' (turned off)
when the inputs change at a composite frequency of less than 15MHz. When the Turbo Bit
is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo Bit affects the
PLD’s DC power, AC power, and propagation delay. When the Turbo mode is off, the
UPSD323xx devices’ input clock frequency is reduced by 5 MHz from the maximum rated
clock frequency.
Blocking MCU control signals with the bits of PMMR2 can further reduce PLD AC power
consumption.
MCU I/O
PLD Out
Address Out
Peripheral I/O
Port Function
No
by setting PMMR0 bits 4 and 5
Disable desired inputs to PLD
and PMMR2 bits 2 through 6.
PSD Module in Power
Set PMMR0 Bit 1 = 1
OPTIONAL
for 15 CLKIN
Enable APD
Down Mode
ALE idle
clocks?
RESET
Yes
No Change
No Change
Undefined
Tri-State
AI06609
Pin Level
Power management
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