UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 70

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Standard serial interface (UART)
12.2.5
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Figure 26
timing.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“WRITE to SBUF” signal at S6P2 also loads a '1' into the 9th position of the transmit shift
register and tells the TX Control block to commence a transmission. The internal timing is
such that one full machine cycle will elapse between “WRITE to SBUF” and activation of
SEND.
SEND enables the output of the shift register to the alternate out-put function line of RxD
and also enable SHIFT CLOCK to the alternate output function line of TxD. SHIFT CLOCK
is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2. At
S6P2 of every machine cycle in which SEND is active, the contents of the transmit shift are
shifted to the right one position.
As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte
is at the output position of the shift register, then the '1' that was initially loaded into the 9th
position, is just to the left of the MSB, and all positions to the left of that contain zeros. This
condition flags the TX Control block to do one last shift and then deactivate SEND and set
T1. Both of these actions occur at S1P1. Both of these actions occur at S1P1 of the 10th
machine cycle after “WRITE to SBUF.”
Reception is initiated by the condition REN = 1 and R1 = 0. At S6P2 of the next machine
cycle, the RX Control unit writes the bits 11111110 to the receive shift register, and in the
next clock phase activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate output function line of TxD. SHIFT
CLOCK makes transitions at S3P1 and S6P1 of every machine cycle in which RECEIVE is
active, the contents of the receive shift register are shifted to the left one position. The value
that comes in from the right is the value that was sampled at the RxD pin at S5P2 of the
same machine cycle.
As data bits come in from the right, '1s' shift out to the left. When the '0' that was initially
loaded into the right-most position arrives at the left-most position in the shift register, it flags
the RX Control block to do one last shift and load SBUF. At S1P1 of the 10th machine cycle
after the WRITE to SCON that cleared RI, RECEIVE is cleared as RI is set.
More about Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a start Bit (0), 8 data bits
(LSB first). and a Stop bit (1). On receive, the Stop bit goes into RB8 in SCON. In the
UPSD323xx devices the baud rate is determined by the Timer 1 or Timer 2 overflow rate.
Figure 28
timings for transmit receive.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“WRITE to SBUF” signal also loads a '1' into the 9th bit position of the transmit shift register
and flags the TX Control unit that a transmission is requested. Transmission actually
commences at S1P1 of the machine cycle following the next rollover in the divide-by-16
counter. (Thus, the bit times are synchronized to the divide-by-16 counter, not to the
“WRITE to SBUF” signal.)
The transmission begins with activation of SEND which puts the start bit at TxD. One bit
time later, DATA is activated, which enables the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time after that.
shows a simplified functional diagram of the serial port in Mode 0, and associated
shows a simplified functional diagram of the serial port in Mode 1, and associated
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV