UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 44

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt system
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External Int1 interrupt
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DDC interrupt
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USB interrupt
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USART interrupt
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The INT1 can be either level active or transition active depending on Bit IT1 in register
TCON. The flag that actually generates this interrupt is Bit IE1 in TCON.
When an external interrupt is generated, the corresponding request flag is cleared by
the hardware when the service routine is vectored to only if the interrupt was transition
activated.
If the interrupt was level activated then the interrupt request flag remains set until the
requested interrupt is actually generated. Then it has to deactivate the request before
the interrupt service routine is completed, or else another interrupt will be generated.
The ADC can take over the External INT1 to generate an interrupt on conversion being
completed
The DDC interrupt is generated either by Bit INTR in the S1STA register for DC2B
protocol or by Bit DDC interrupt in the DDCCON register for DDC1 protocol or by Bit
SWHINT Bit in the DDCCON register when DDC protocol is changed from DDC1 to
DDC2.
Flags except the INTR have to be cleared by the software. INTR flag is cleared by
hardware.
The USB interrupt is generated when endpoint0 has transmitted a packet or received a
packet, when Endpoint1 or Endpoint2 has transmitted a packet, when the suspend or
resume state is detected and every EOP received.
When the USB interrupt is generated, the corresponding request flag must be cleared
by software. The interrupt service routine will have to check the various USB registers
to determine the source and clear the corresponding flag.
Please see the dedicated interrupt control registers for the USB peripheral for more
information.
The USART Interrupt is generated by RI (receive interrupt) OR TI (transmit interrupt).
When the USART Interrupt is generated, the corresponding request flag must be
cleared by software. The interrupt service routine will have to check the various USART
registers to determine the source and clear the corresponding flag.
Both USART’s are identical, except for the additional interrupt controls in the Bit 4 of the
additional interrupt control registers (A7h, B7h)
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV