UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 83

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
14.3
PWM 4-channel operation
The 16-bit Prescaler1 divides the input clock (f
clock runs the 8-bit Counter of the PWM 4 channel. The input clock frequency to the PWM 4
Counter is:
When the Prescaler1 Register (B4h, B3h) is set to data value '0,' the maximum input clock
frequency to the PWM 4 Counter is f
The PWM 4 Counter is a free-running, 8-bit counter. The output of the counter is compared
to the Compare Registers, which are loaded with data from the Pulse Width Register
(PWM4W, ABh) and the Period Register (PWM4P, AAh). The Pulse Width Register defines
the pulse duration or the Pulse Width, while the Period Register defines the period of the
PWM. When the PWM 4 channel is enabled, the register values are loaded into the
Comparator Registers and are compared to the Counter output. When the content of the
counter is equal to or greater than the value in the Pulse Width Register, it sets the PWM 4
output to low (with PWMP Bit = 0). When the Period Register equals to the PWM4 Counter,
the Counter is cleared, and the PWM 4 channel output is set to logic 'high' level (beginning
of the next PWM pulse).
The Period Register cannot have a value of “00” and its content should always be greater
than the Pulse Width Register.
The Prescaler1 Register, Pulse Width Register, and Period Register can be modified while
the PWM 4 channel is active. The values of these registers are automatically loaded into the
Prescaler Counter and Comparator Registers when the current PWM 4 period ends.
The PWMCON Register (Bits 5 and 6) controls the enable/disable and polarity of the PWM 4
channel.
Figure 37. PWM 4 with programmable pulse width and frequency
f PWM4 = (f
PWM4
OSC
/2)/(Prescaler1 data value +1)
Defined by Pulse
Width Register
OSC
Defined by Period Register
/2 and can be as high as 20MHz.
Switch Level
OSC
/2) to the desired frequency, the resulting
Pulse width modulation (PWM)
RESET
Counter
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