UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 85

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Table 50.
Table 51.
Table 52.
CR2
CR2
Bit
7
7
6
5
4
3
2
1
0
0
0
0
0
1
1
Serial control register (SxCON: S1CON, S2CON)
Description of the SxCON bits
Selection of the serial clock frequency SCL in Master mode
Symbol
ADDR
CR2
STO
CR1
CR0
CR1
ENII
ENII
STA
AA
6
0
0
1
1
0
0
This bit along with Bits CR1and CR0 determines the serial clock frequency
when SIO is in the Master mode.
Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are
in the high impedance state.
START flag. When this bit is set, the SIO H/W checks the status of the I
bus and generates a START condition if the bus free. If the bus is busy, the
SIO will generate a repeated START condition when this bit is set.
STOP flag. With this bit set while in Master mode a STOP condition is
generated.
When a STOP condition is detected on the I
clears the STO flag.
Note: This bit have to be set before 1 cycle interrupt period of STOP. That
is, if this bit is set, STOP condition in Master mode is generated after 1
cycle interrupt period.
This bit is set when address byte was received. Must be cleared by
software.
Acknowledge enable signal. If this bit is set, an acknowledge (low level to
SDA) is returned during the acknowledge clock pulse on the SCL line
when:
• Own slave address is received
• A data byte is received while the device is programmed to be a Master
Receiver
• A data byte is received while the device is a selected Slave Receiver.
When this bit is reset, no acknowledge is returned.
SIO release SDA line as high during the acknowledge clock pulse.
These two bits along with the CR2 Bit determine the serial clock frequency
when SIO is in the Master mode.
CR0
STA
5
0
1
0
1
0
1
divisor
f
STO
120
240
OSC
16
24
30
60
4
12 MHz
ADDR
375
250
200
100
50
25
3
Function
Bit rate (kHz) at f
24 MHz
750
500
400
200
100
AA
50
2
2
C-bus, the I
36 MHz
CR1
750
600
300
150
75
X
1
2
OSC
C hardware
I
2
C interface
40 MHz
CR0
833
666
333
166
83
X
0
85/189
2
C-