UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 160

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

EMC characteristics
31.3
31.3.1
31.3.2
31.3.3
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Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU, and DLU) and using specific measurement
methods, the product is stressed in order to determine its performance in terms of electrical
sensitivity. For more details, refer to the Application Note AN1181.
Electro-static discharge (ESD)
Electro-Static discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). The Human
Body Model is simulated
Table 110. EMS test results
1. Data based on characterization results, not tested in production.
Table 111. ESD absolute maximum ratings
1. Data based on characterization results, not tested in production
Latch-up
3 complementary static tests are required on 10 parts to assess the latch-up performance. A
supply overvoltage (applied to each power supply pin) and a current injection (applied to
each input, output, and configurable I/O pin) are performed on each sample. This test
conforms to the EIA/JESD 78 IC Latch-up Standard (see
to the Application Note, AN1181.
Dynamic latch-up
Electro-static discharges (one positive then one negative test) are applied to each pin of 3
samples when the micro is running to assess the latch-up performance in dynamic mode.
Power supplies are set to the typical values, the oscillator is connected as near as possible
to the pins of the micro, and the component is put in reset mode. This test conforms to the
IEC 1000-4-2 and SAEJ1752/3 Standards (see
Application Note, AN1181.
Table 112. Latch-up and dynamic latch-up electrical sensitivities
1. Class description: A Class is an STMicroelectronics internal specification. All of its limits are higher than the
Symbol
V
Symbol
V
Symbol
ESD(HBM)
DLU
JEDEC specifications. This means when a device belongs to “Class A,” it exceeds the JEDEC standard.
“Class B” strictly covers all of the JEDEC criteria (International standards).
LU
FESD
Static latch-up class
Dynamic latch-up class
Voltage limits to be applied on any
I/O pin to induce a functional
disturbance
Electro-static discharge voltage
(Human Body Model)
Parameter
Parameter
Parameter
(Table
111). This test complies with the JESD22-A114A Standard.
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
T
V
A
DD
= 25°C
= 5 V; T
V
40MHz; WDT off complies with
IEC 1000-4-2
DD
A
Conditions
Table
= 4V; T
T
= 25°C; f
A
= 25°C
Conditions
Conditions
112). For more details, refer to the
A
= 25°C; f
OSC
Table
= 40 MHz
112). For more details, refer
OSC
Max. Value
=
2000
(1)
Level/Class
Level/class
3C
Unit
A
A
V
(1)
(1)