UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 99

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
Table 72.
Table 73.
Table 74.
3 to 0
7 to 5
Bit
Bit
—
7
6
5
4
7
4
3
EP12SEL
Description of the UCON1 bits
FRESUM
USB control register (UCON2: 0ECh)
Description of the UCON2 bits
TP1SIZ3
TP1SIZ0
Symbol
Symbol
TSEQ1
SOUT
EP2E
TX1E
—
—
to
6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
5
Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0,
1=DATA1) This bit determines which type of data packet
(DATA0 or DATA1) will be sent during the next IN transaction
directed to Endpoint 1 or Endpoint 2.
Toggling of this bit must be controlled by software. RESET
clears this bit.
Endpoint 1/ Endpoint 2 Transmit Selection. (0=Endpoint 1,
1=Endpoint 2)
This bit specifies whether the data inside the registers UDT1
are used for Endpoint 1 or Endpoint 2. If all the conditions for a
successful Endpoint 2 USB response to a hosts IN token are
satisfied (TXD1F=0, TX1E=1, STALL2=0, and EP2E=1)
except that the EP12SEL Bit is configured for Endpoint 1, the
USB responds with a NAK handshake packet. RESET clears
this bit.
Endpoint1 / Endpoint2 Transmit Enable.
This bit enables a transmit to occur when the USB Host
Controller send an IN token to Endpoint 1 or Endpoint 2. The
appropriate endpoint enable bit, EP1E or EP2E Bit in the
UCON2 register, should also be set. Software should set the
TX1E Bit when data is ready to be transmitted. It must be
cleared by software when no more data needs to be
transmitted. If this bit is '0' or TXD1F is set, the USB will
respond with a NAK handshake to any Endpoint 1 or Endpoint
2 directed IN token.
RESET clears this bit.
Force Resume.
This bit forces a resume state (“K” on non-idle state) on the
USB data lines to initiate a remote wake-up. Software should
control the timing of the forced resume to be between 10ms
and 15ms. Setting this bit will not cause the RESUMF Bit to
set.
The number of transmit data bytes. These bits are cleared by
RESET.
Reserved
Status out is used to automatically respond to the OUT of a
control READ transfer
Endpoint2 enable. RESET clears this bit
SOUT
4
EP2E
3
Function
Function
EP1E
2
STALL2
1
USB hardware
STALL1
0
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