UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 148

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Power management
25.2
25.3
25.4
148/189
PSD chip select input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select Input (CSI). When
Low, the signal selects and enables the PSD module Flash memory, SRAM, and I/O blocks
for READ or WRITE operations. A High on PSD Chip Select Input (CSI, PD2) disables the
Flash memory, and SRAM, and reduces power consumption. However, the PLD and I/O
signals remain operational when PSD Chip Select Input (CSI, PD2) is High.
Input clock
CLKIN (PD1) can be turned off, to the PLD to save AC power consumption. CLKIN (PD1) is
an input to the PLD AND Array and the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic
equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from
the PLD AND Array or the Macrocells block by setting Bits 4 or 5 to a '1' in PMMR0.
Input control signals
The PSD module provides the option to turn off the MCU signals (WR, RD, PSEN, and
Address Strobe (ALE)) to the PLD to save AC power consumption. These control signals
are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being
used as part of the PLD logic equation, these control signals should be disabled to save AC
power. They are disconnected from the PLD AND Array by setting Bits 2, 3, 4, 5, and 6 to a
'1' in PMMR2.
Table 103. Power management mode registers (PMMR0)
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
X
APD Enable
X
PLD Turbo
PLD Array
clk
PLD MCell
clk
X
X
0
0 = off
1 = on
0
0 = on
1 = off
0 = on
1 = off
0 = on
1 = off
0
0
Not used, and should be set to zero.
Automatic Power-down (APD) is disabled.
Automatic Power-down (APD) is enabled.
Not used, and should be set to zero.
PLD Turbo mode is on
PLD Turbo mode is off, saving power.
UPSD323xx devices operate at 5MHz below the maximum rated
clock frequency
CLKIN (PD1) input to the PLD AND Array is connected. Every
change of CLKIN (PD1) Powers-up the PLD when Turbo Bit is '0.'
CLKIN (PD1) input to PLD AND Array is disconnected, saving
power.
CLKIN (PD1) input to the PLD macrocells is connected.
CLKIN (PD1) input to PLD macrocells is disconnected, saving
power.
Not used, and should be set to zero.
Not used, and should be set to zero.
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV