UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 145

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
25
Power management
All PSD modules offer configurable power saving options. These options may be used
individually or in combinations, as follows:
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The primary and secondary Flash memory, and SRAM blocks are built with power
management technology. In addition to using special silicon design methodology,
power management technology puts the memories into Standby mode when
address/data inputs are not changing (zero DC current). As soon as a transition occurs
on an input, the affected memory “wakes up,” changes and latches its outputs, then
goes back to standby. The designer does not have to do anything special to achieve
Memory Standby mode when no inputs are changing—it happens automatically.
The PLD sections can also achieve Standby mode when its inputs are not changing, as
described in the sections on the Power Management mode Registers (PMMR).
As with the Power Management mode, the Automatic Power Down (APD) block allows
the PSD module to reduce to Standby current automatically. The APD Unit can also
block MCU address/data signals from reaching the memories and PLDs.
Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity
for a certain time period (MCU is asleep), the APD Unit initiates Power-down mode (if
enabled). Once in Power-down mode, all address/data signals are blocked from
reaching memory and PLDs, and the memories are deselected internally. This allows
the memory and PLDs to remain in Standby mode even if the address/data signals are
changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind
that any unblocked PLD input signals that are changing states keeps the PLD out of
Standby mode, but not the memories.
PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories,
placing them in Standby mode even if inputs are changing. This feature does not block
any internal signals or disable the PLDs. This is a good alternative to using the APD
Unit. There is a slight penalty in memory access time when PSD Chip Select Input
(CSI, PD2) makes its initial transition from deselected to selected.
The PMMRs can be written by the MCU at run-time to manage power. The PSD
module supports “blocking bits” in these registers that are set to block designated
signals from reaching both PLDs. Current consumption of the PLDs is directly related
to the composite frequency of the changes on their inputs (see Figure
Figure
used in DPLD or CPLD logic equations.
71). Significant power savings can be achieved by blocking signals that are not
Power management
Figure 70
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and