UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 59

• Manufacturer Part Number: UPSD3234A-40U6T
• Description: IC MCU 8032 64KB FLASH 80TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3234A-40U6T

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, UART/USART, USB
• Peripherals: LVR, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 288KB (288K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Timer/counters (Timer 0, Timer 1 and Tim-
11
11.1
Timer/counters (Timer 0, Timer 1 and Timer 2)
The UPSD323xx devices has three 16-bit Timer/Counter registers: Timer 0, Timer 1 and
Timer 2. All of them can be configured to operate either as timers or event counters and are
compatible with standard 8032 architecture.
In the “Timer” function, the register is incremented every machine cycle. Thus, one can think
of it as counting machine cycles. Since a machine cycle consists of 6 CPU clock periods,
the count rate is 1/6 of the CPU clock frequency or 1/12 of the oscillator frequency (f
In the “Counter” function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples show a high in one cycle and a low
in the next cycle, the count is incremented. The new count value appears in the register
during S3P1 of the cycle following the one in which the transition was detected. Since it
takes 2 machine cycles (24 f
maximum count rate is 1/24 of the f
external input signal, but to ensure that a given level is sampled at least once before it
changes, it should be held for at least one full cycle. In addition to the “Timer” or “Counter”
selection, Timer 0 and Timer 1 have four operating modes from which to select.
Timer 0 and Timer 1
The “Timer” or “Counter” function is selected by control bits C/ T in the Special Function
Register TMOD. These Timer/Counters have four operating modes, which are selected by
bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for Timers/ Counters. Mode 3
is different. The four operating modes are de-scribed in the following text.
Table 36.
Table 37.
TF1
Bit
7
7
6
5
4
3
2
Control register (TCON)
Description of the TCON bits
Symbol
TR1
TR1
TR0
TF1
TF0
IE1
IT1
6
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared
by hardware when processor vectors to interrupt routine
Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on or
off
Timer 0 overflow flag. Set by hardier on Timer/Counter overflow. Cleared by
hardware when processor vectors to interrupt routine
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on or
off
Interrupt 1 Edge Flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed
Interrupt 1 Type Control Bit. Set/cleared by software to specify falling-
edge/low-level triggered external interrupt
TF0
5
OSC
clock periods) to recognize a 1-to-0 transition, the
OSC
TR0
. There are no restrictions on the duty cycle of the
4
IE1
3
Function
IT1
2
IE0
1
OSC
IT0
0
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).