UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 135

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
(6) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 clock oscillation stabilization time counter.
oscillation clock or subsystem clock is used as the CPU clock, the X1 clock oscillation stabilization time can be
checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, and WDT), the STOP instruction and MSTOP (bit 7 of
MOC register) = 1 clear OSTC to 00H.
Address: FFA3H
Symbol
OSTC
Figure 6-7. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Remark f
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
MOST11
7
0
1
1
1
1
1
After reset: 00H
2. If the STOP mode is entered and then released while the internal high-speed
3. The X1 clock oscillation stabilization wait time does not include the time until
X
: X1 clock oscillation frequency
MOST13
remain 1.
oscillation clock or subsystem clock is being used as the CPU clock, set the
oscillation stabilization time as follows.
The oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
clock oscillation starts (“a” below).
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set
by OSTS
6
0
0
1
1
1
1
X1 pin voltage
waveform
R
CHAPTER 6 CLOCK GENERATOR
MOST14
User’s Manual U17554EJ4V0UD
5
0
0
0
1
1
1
STOP mode release
MOST11
MOST15
4
0
0
0
1
1
a
MOST13
MOST16
3
0
0
0
0
1
2
2
2
2
2
11
13
14
15
16
MOST14
Oscillation stabilization time status
/f
/f
/f
/f
/f
X
X
X
X
X
2
min.
min.
min.
min.
min.
204.8
819.2
1.64 ms min. 819.2
3.27 ms min. 1.64 ms min.
6.55 ms min. 3.27 ms min.
f
X
MOST15
If the internal high-speed
= 10 MHz
1
μ
μ
s min. 102.4
s min. 409.6
f
X
MOST16
= 20 MHz
0
μ
μ
μ
s min.
s min.
s min.
135

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