UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 214

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
214
Caution Do not set the CR00n and CR01n registers to 0000H.
Remark n = 0 to 3
TMC0n
TOC0n
CRC0n
PRM0n
Figure 7-51. Control Register Settings for One-Shot Pulse Output with External Trigger
ES1n1
7
0
0/1
7
0
7
0
OSPT0n
ES1n0
0
0/1
6
0
6
0
OSPE0n
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03
(c) 16-bit timer output control register 0n (TOC0n)
(a) 16-bit timer mode control register 0n (TMC0n)
(b) Capture/compare control register 0n (CRC0n)
ES0n1
1
5
0
5
0
0
(d) Prescaler mode register 0n (PRM0n)
TOC0n4
ES0n0
1
(with Rising Edge Specified)
4
0
1
4
0
User’s Manual U17554EJ4V0UD
LVS0n
TMC0n3
0/1
1
3
0
3
0
LVR0n
0/1
TMC0n2 TMC0n1
CRC0n2 CRC0n1 CRC0n0
0
0
2
0
TOC0n1
1
PRM0n1 PRM0n0
0/1
0/1
0
TOE0n
1
OVF0n
0/1
0
0
Enables TO0n output.
Inverts output upon match
between TM0n and CR00n.
Specifies initial value of
TO0n output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM0n and CR01n.
Sets one-shot pulse output mode.
Clears and starts at
valid edge of TI00n pin.
CR00n used as compare register
CR01n used as compare register
Selects count clock
(setting “11” is prohibited).
Specifies the rising edge
for pulse width detection.
Setting invalid
(setting “10” is prohibited.)

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