UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 425

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
(4) CAN global automatic block transmission delay setting register (C0GMABTD)
The C0GMABTD register is used to set the interval at which the data of the message buffer assigned to ABT
is to be transmitted in the normal operation mode with ABT.
After reset: 00H
Cautions 1. Do not change the contents of the C0GMABTD register while the ABTTRG bit
ABTD3
C0GMABTD
0
0
0
0
0
0
0
0
1
2. The timing at which the ABT message is actually transmitted onto the CAN
ABTD2
Other than above
0
0
0
0
1
1
1
1
0
is set to 1.
bus differs depending on the status of transmission from the other station or
how a request to transmit a message other than an ABT message (message
buffers 8 to 15) is made.
0
7
ABTD1
0
0
1
1
0
0
1
1
0
R/W
6
0
ABTD0
CHAPTER 16 CAN CONTROLLER
Address: FF6FH
0
1
0
1
0
1
0
1
0
User’s Manual U17554EJ4V0UD
5
0
Data frame interval during automatic block transmission (unit:
Data bit time (DBT))
0 DBT (default value)
2
2
2
2
2
2
2
2
Setting prohibited
5
6
7
8
9
10
11
12
DBT
DBT
DBT
DBT
DBT
DBT
DBT
DBT
4
0
ABTD3
3
ABTD2
2
ABTD1
1
ABTD0
0
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