UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 288

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
13.3 Registers Used in A/D Converter
(1) A/D converter mode register (ADM)
288
The A/D converter uses the following seven registers.
• A/D converter mode register (ADM)
• A/D port configuration register (ADPC)
• Analog input channel specification register (ADS)
• Port mode register 8 (PM8)
• Port mode register 9 (PM9)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Notes 1. For details of FR2 to FR0, LV1, LV0, and A/D conversion, see Table 13-2 A/D Conversion Time
Symbol
Address: FF2AH
ADM
2. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1
Selection.
start to operation stabilization. Therefore, when ADCS is set to 1 after 1
from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion
result. Otherwise, ignore data of the first conversion.
ADCS
ADCE
ADCS
<7>
0
1
0
1
Figure 13-3. Format of A/D Converter Mode Register (ADM)
After reset: 00H
Stops conversion operation
Enables conversion operation
Stops comparator operation
Enables comparator operation (comparator: 1/2AV
6
0
FR2
CHAPTER 13 A/D CONVERTER
User’s Manual U17554EJ4V0UD
5
R/W
Note 1
FR1
A/D conversion operation control
Comparator operation control
4
Note 1
FR0
3
Note 1
REF
LV1
operation)
2
Note 1
Note 2
LV0
1
Note 1
μ
s or more has elapsed
ADCE
<0>
μ
s from operation

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