UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 287

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
<R>
<R>
(7) 8-bit A/D conversion result register (ADCRH)
(8) Controller
(9) AV
(10) AV
(11) A/D converter mode register (ADM)
(12) A/D port configuration register (ADPC)
(13) Analog input channel specification register (ADS)
(14) Port mode register 8 (PM8)
(15) Port mode register 9 (PM9)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as
well as starting and stopping of the conversion operation. When A/D conversion has been completed, this
controller generates INTAD.
This pin inputs an analog power/reference voltage to the A/D converter. Make this pin the same potential as the
V
The signal input to ANI0 to ANI11 is converted into a digital signal, based on the voltage applied across AV
and AV
This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the V
pin even when the A/D converter is not used.
This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the
conversion operation.
This register switches the P80/ANI0 to P87/ANI7, P90/ANI8 to P93/ANI11 pins to analog input of A/D converter or
digital I/O of port.
This register is used to specify the port that inputs the analog voltage to be converted into a digital signal.
This register switches the P80/ANI0 to P87/ANI7 pins to input or output.
This register switches the P90/ANI8 to P93/ANI11 pins to input or output.
DD
Caution When data is read from ADCR and ADCRH, a wait cycle is generated. Do not read data from
REF
SS
pin when port 8 and port 9 are used as a digital port.
pin
pin
SS
.
ADCR and ADCRH when the CPU is operating on the subsystem clock and the peripheral
hardware clock is stopped. For details, see CHAPTER 31 CAUTIONS FOR WAIT.
CHAPTER 13 A/D CONVERTER
User’s Manual U17554EJ4V0UD
287
REF
SS

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