UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 598

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
598
Address: 0081H/1081H
Address: 0082H/1082H, 0083H/1083H
Address: 0084H/1084H
Notes 1.
Caution Be sure to clear bits 7 to 1 to “0”.
Note Be sure to set 00H to 0082H and 0083H, as these addresses are reserved areas. Also set 00H to 1082H
Note
Remark For the on-chip debug security ID, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
and 1083H because 0082H and 0083H are switched with 1082H and 1083H when the boot swap operation
is used.
2.
To use the on-chip debug function, set 02H or 03H to 0084H. Set a value that is the same as that of 0084H
to 1084H because 0084H and 1084H are switched during the boot swap operation.
LVISTART
LVISTART can only be written by using a dedicated flash memory programmer. It cannot be set during
self-programming or boot swap operation during self-programming (at this time, 1.59 V POC mode
(default) is set). However, because the value of 1081H is copied to 0081H during the boot swap
operation, it is recommended to set a value that is the same as that of 0081H to 1081H when the boot
swap function is used.
To change the setting for the POC mode, set the value to 0081H again after batch erasure (chip
erasure) of the flash memory. The setting cannot be changed after the memory of the specified block
is erased.
OCDEN1
7
0
0
1
7
0
7
0
0
0
1
1
Notes 1, 2
Note
1.59 V POC mode (default)
2.7 V/1.59 V POC mode
OCDEN0
6
0
6
0
6
0
0
1
0
1
Note
Figure 23-1. Format of Option Byte (2/2)
Operation disabled
Setting prohibited
Operation enabled. Does not erase data of the flash memory in case authentication
of the on-chip debug security ID fails.
Operation enabled. Erases data of the flash memory in case authentication of the
on-chip debug security ID fails.
CHAPTER 23 OPTION BYTE
5
0
5
0
5
0
User’s Manual U17554EJ4V0UD
4
0
4
0
4
0
POC mode selection
On-chip debug operation control
3
0
3
0
3
0
2
0
2
0
2
0
OCDEN1
1
0
1
0
1
LVISTART
OCDEN0
0
0
0
0

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