UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 477

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

16.12 Interrupt Function
signals are generated from the six interrupt sources. When an interrupt request signal that corresponds to two or
more interrupt sources is generated, the interrupt sources can be identified by using an interrupt status register. After
an interrupt source has occurred, the corresponding interrupt status bit must be cleared to 0 by software.
Note The IE bit (message buffer interrupt enable bit) in the C0MCTRL register of the corresponding message buffer
Supplements 1. This interrupt is generated when the transmission/reception error counter is at the warning level, or
Remark
No.
1
2
3
4
5
6
The CAN module provides 6 different interrupt sources.
The occurrence of these interrupt sources is stored in interrupt status registers. Four separate interrupt request
CINTS0
CINTS1
CINTS2
CINTS3
CINTS4
CINTS5
has to be set to 1 for that message buffer to participate in the interrupt generation process.
Name
Interrupt Status Bit
m = 0 to 15
2. This interrupt is generated when a stuff error, form error, ACK error, bit error, or CRC error occurs.
3. This interrupt is generated when the CAN module is woken up from the CAN sleep mode because
Note
Note
in the error passive or bus-off state.
a falling edge is detected at the CAN reception pin (CAN bus transition from recessive to
dominant).
C0INTS
C0INTS
C0INTS
C0INTS
C0INTS
C0INTS
Register
Table 16-20. List of CAN Module Interrupt Sources
CIE0
CIE1
CIE2
CIE3
CIE4
CIE5
Name
Interrupt Enable Bit
Note
Note
CHAPTER 16 CAN CONTROLLER
User’s Manual U17554EJ4V0UD
C0IE
C0IE
C0IE
C0IE
C0IE
C0IE
Register
INTC0TRX
INTC0REC
INTC0ERR
INTC0WUP
Request Signal
Interrupt
Message frame successfully transmitted
from message buffer m
Valid message frame reception in
message buffer m
CAN module error state interrupt
(Supplement 1)
CAN module protocol error interrupt
(Supplement 2)
CAN module arbitration loss interrupt
CAN module wakeup interrupt from CAN
sleep mode (Supplement 3)
Interrupt Source Description
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