UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 273

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
11.2 Configuration of Watchdog Timer
WINDOW1 and WINDOW0
The watchdog timer includes the following hardware.
How the counter operation is controlled, overflow time, and window open period are set by the option byte.
of option byte (0080H)
of option byte (0080H)
CPU access signal
WDCS2 to WDCS0
Remark For the option byte, see CHAPTER 23 OPTION BYTE.
f
Window open period
Controlling counter operation of watchdog timer
Overflow time of watchdog timer
RL
/2
WDTON of
option byte
Control register
(0080H)
Setting of Watchdog Timer
controller
Clock
input
Item
Table 11-2. Setting of Option Bytes and Watchdog Timer
Watchdog timer enable
register (WDTE)
Figure 11-1. Block Diagram of Watchdog Timer
Clear, reset control
Table 11-1. Configuration of Watchdog Timer
counter
17-bit
CHAPTER 11 WATCHDOG TIMER
Watchdog timer enable register (WDTE)
Count clear
signal
User’s Manual U17554EJ4V0UD
2
2
10
17
error detector
CPU access
/f
/f
RL
RL
Internal bus
to
determination
Selector
Window size
Bits 6 and 5 (WINDOW1, WINDOW0)
Bit 4 (WDTON)
Bits 3 to 1 (WDCS2 to WDCS0)
signal
Configuration
Overflow
signal
Option Byte (0080H)
controller
output
Reset
Internal reset signal
273

Related parts for UPD78F0890GK(A)-GAJ-AX