UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 327

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(5) Baud rate generator control register 6n (BRGC6n)
Address: FF57H After reset: FFH R/W
BRGC60
Cautions 1. Make sure that bit 6 (TXE60) and bit 5 (RXE60) of the ASIM6n register = 0 when rewriting the
Remarks 1.
Symbol
This register sets the division value of the 8-bit counters of serial interface UART60 and UART61.
BRGC6n can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Remark BRGC6n can be refreshed (the same value is written) by software during a communication
2. The baud rate is the output clock of the 8-bit counter divided by 2.
2.
3.
MDL670 MDL660 MDL650 MDL640 MDL630 MDL620 MDL610 MDL600
MDL670 MDL660 MDL650 MDL640 MDL630 MDL620 MDL610 MDL600
operation (when bits 7 and 6 (POWER6n, TXE6n) of ASIM6n = 1 or bits 7 and 5 (POWER6n,
RXE6n) of ASIM6n = 1).
7
0
0
0
0
1
1
1
1
•
•
•
•
•
MDL670 to MDL600 bits.
f
k: Value set by MDL670 to MDL600 bits (k = 4, 5, 6, ..., 255)
×: Don’t care
Figure 14-15. Format of Baud Rate Generator Control Register 60 (BRGC60)
XCLK6
: Frequency of base clock selected by the TPS630 to TPS600 bits of CKSR60 register
6
0
0
0
0
1
1
1
1
•
•
•
•
•
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
5
0
0
0
0
1
1
1
1
•
•
•
•
•
4
0
0
0
0
1
1
1
1
•
•
•
•
•
User’s Manual U17554EJ4V0UD
3
0
0
0
0
•
•
•
•
•
1
1
1
1
2
0
1
1
1
1
1
1
1
•
•
•
•
•
1
×
0
0
1
0
0
1
1
•
•
•
•
•
0
×
0
1
0
•
•
•
•
•
0
1
0
1
252
253
254
255
k
×
4
5
6
•
•
•
•
•
Setting prohibited
f
f
f
f
f
f
f
XCLK6
XCLK6
XCLK6
XCLK6
XCLK6
XCLK6
XCLK6
Output clock selection of
/4
/5
/6
/252
/253
/254
/255
8-bit counter
•
•
•
•
•
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