UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 145

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

6.6 Controlling Clock
6.6.1 Controlling high-speed system clock
pins.
remark
The following two types of high-speed system clocks are available.
• X1 clock:
• External main system clock: External clock is input to the EXCLK pin.
When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port
The following describes examples of setting procedures for the following cases.
(1) When oscillating X1 clock
(2) When using external main system clock
(3) When using high-speed system clock as CPU clock and peripheral hardware clock
(4) When stopping high-speed system clock
(1) Example of setting procedure when oscillating the X1 clock
Caution The X1/P121 and X2/EXCLK/P122 pins are in the I/O port mode after a reset release.
<1> Setting frequency (OSCCTL register)
<2> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register)
<3> Controlling oscillation of X1 clock (MOC register)
Using AMPH, set the gain of the on-chip oscillator according to the frequency to be used.
Note Set AMPH before setting the peripheral functions after a reset release. The value of AMPH can
Remark f
When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1
oscillation mode.
If MSTOP is cleared to 0, the X1 oscillator starts oscillating.
The clock which is not used as a CPU clock can be suspended by setup of software during
microcomputer operation. Moreover, high-speed oscillation clock and a high-speed system clock can
suspend a clock by execution of a STOP command (see (4) in 6.6.1 Controlling high-speed system
clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 6.6.3
Example of controlling subsystem clock).
AMPH
EXCLK
0
1
0
be changed only once after a reset release. When AMPH is set to 1, the clock supply to the CPU
is stopped for 4.06 to 16.12
Note
XH
4 MHz ≤ f
10 MHz < f
: High-speed system clock oscillation frequency
OSCSEL
1
Crystal/ceramic resonator is connected across the X1 and X2 pins.
XH
XH
X1 oscillation mode
≤ 10 MHz
Operation Mode of High-
Speed System Clock Pin
≤ 20 MHz
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17554EJ4V0UD
μ
s.
Operating Frequency Control
Crystal/ceramic resonator connection
P121/X1 Pin
P122/X2/EXCLK Pin
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