UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 61

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
3.2.3 Special Function Registers (SFRs)
manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.
Unlike a general-purpose register, each special function register has a special function.
SFRs are allocated to the FF00H to FFFFH area.
Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
• 8-bit manipulation
• 16-bit manipulation
Table 3-8 gives a list of the special function registers. The meanings of items in the table are as follows.
• Symbol
• R/W
• Manipulatable bit units
• After reset
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When specifying an address, describe an even address.
Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is defined
by the header file “sfrbit.h” in the CC78K0. When using the RA78K0, ID78K0-NS, ID78K0, or SM78K0, symbols
can be written as an instruction operand.
Indicates whether the corresponding special function register can be read or written.
R/W: Read/write enable
R:
W:
Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.
Indicates each register status upon reset signal generation.
Read only
Write only
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U17554EJ4V0UD
61

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