UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 169

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(4) Setting range when CR00n or CR01n is used as a compare register
Operation as interval timer
Operation as square-wave output
Operation as external event counter
Operation in the clear & start mode
entered by TI00n pin valid edge input
Operation as free-running timer
Operation as PPG output
Operation as one-shot pulse output
Note When 0000H is set, a match interrupt immediately after the timer operation does not occur and timer output
Remarks 1. N: CR00n register set value, M: CR01n register set value
When CR00n or CR01n is used as a compare register, set it as shown below.
is not changed, and the first match timing is as follows. A match interrupt occurs at the timing when the
timer counter (TM0n register) is changed from 0000H to 0001H.
• When the timer counter is cleared due to overflow
• When the timer counter is cleared due to TI00n pin valid edge (when clear & start mode is entered by
• When the timer counter is cleared due to compare match (when clear & start mode is entered by match
TI00n pin valid edge input)
between TM0n and CR00n (CR00n = other than 0000H, CR01n = 0000H))
2. For details of TMC0n3 and TMC0n2, see 7.3 (1) 16-bit timer mode control register 0n (TMC0n).
3. n = 0 to 3
Operation
Compare register set value
Timer operation enable bit
Interrupt request signal
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03
(TMC0n3, TMC0n2)
TM0n register
(0000H)
0000H < N ≤ FFFFH
0000H
M < N ≤ FFFFH
0000H
CR00n Register Setting Range
User’s Manual U17554EJ4V0UD
Note
Note
disabled (00)
≤ N ≤ FFFFH
≤ N ≤ FFFFH (N ≠ M)
Operation
is not generated
Interrupt signal
Timer counter clear
Operation enabled
(other than 00)
0000H
Normally, this setting is not used. Mask the
match interrupt signal (INTTM01n).
0000H
0000H
0000H
Interrupt signal
is generated
Note
Note
Note
Note
CR01n Register Setting Range
≤ M ≤ FFFFH
≤ M ≤ FFFFH
≤ M < N
≤ M ≤ FFFFH (M ≠ N)
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