UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 640

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

640
8-bit
operation
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Instruction
Group
2.
3.
2. This clock cycle applies to the internal ROM program.
OR
XOR
CMP
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
Mnemonic
register (PCC).
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 26 INSTRUCTION SET
Note 3
Note 3
Note 3
User’s Manual U17554EJ4V0UD
Bytes
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
−
8
−
−
5
9
5
9
9
9
−
8
−
−
5
9
5
9
9
9
−
8
−
−
5
9
5
9
9
9
A ← A ∨ byte
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
r ← r ∨ A
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A ← A ∨ (HL + byte)
A ← A ∨ (HL + B)
A ← A ∨ (HL + C)
A ← A ∨ byte
(saddr) ← (saddr) ∨ byte
A ← A ∨ r
r ← r ∨ A
A ← A ∨ (saddr)
A ← A ∨ (addr16)
A ← A ∨ (HL)
A ← A ∨ (HL + byte)
A ← A ∨ (HL + B)
A ← A ∨ (HL + C)
A − byte
(saddr) − byte
A − r
r − A
A − (saddr)
A − (addr16)
A − (HL)
A − (HL + byte)
A − (HL + B)
A − (HL + C)
CPU
) selected by the processor clock control
Operation
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×