UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 533

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

17.4.3 Multiple interrupt servicing
(IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0).
Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during
interrupt servicing to enable interrupt acknowledgement.
interrupt priority control. Two types of priority control are available: default priority control and programmable priority
control. Programmable priority control is used for multiple interrupt servicing.
currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority
lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged
for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled
state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the
pending interrupt request is acknowledged following execution of at least one main processing instruction execution.
shows multiple interrupt servicing examples.
Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to
In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt
Table 17-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 17-10
Table 17-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
Remarks 1.
Interrupt Being Serviced
Maskable interrupt
Software interrupt
2. ×: Multiple interrupt servicing disabled
3. ISP and IE are flags contained in the PSW.
4. PR is a flag contained in PR0L, PR0H, PR1L, and PR1H.
Multiple Interrupt Request
ISP = 0: An interrupt with higher priority is being serviced.
ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower
IE = 0:
IE = 1:
PR = 0: Higher priority level
PR = 1: Lower priority level
: Multiple interrupt servicing enabled
priority is being serviced.
Interrupt request acknowledgement is disabled.
Interrupt request acknowledgement is enabled.
ISP = 0
ISP = 1
CHAPTER 17 INTERRUPT FUNCTIONS
During Interrupt Servicing
User’s Manual U17554EJ4V0UD
IE = 1
PR = 0
Maskable Interrupt Request
IE = 0
×
×
×
IE = 1
×
PR = 1
IE = 0
×
×
×
Software
Interrupt
Request
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