UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 725

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

3rd
Edition
• Change of Figure 14-15 and Remark 2
• Change of Figure 14-16 and Remark 2
• Change of Table 14-4 and Remark
• Change of Figure 15-1
• Addition of Remark
• Change of Figure 15-2
• Addition of Remark
Change of Caution 2 in (1) Transmit buffer register 1n (SOTB1n) and (2) Serial I/O shift register 1n (SIO1n)
Addition of Caution 4 and 5 in Figure 14-7. Format of Asynchronous Serial Interface Operation Mode Register
60 (ASIM60) (2/2)
Change of Note 1 in Figure 14-8. Format of Asynchronous Serial Interface Operation Mode Register 61
(ASIM61) (1/2)
Addition of Caution 4 and 5 in Figure 14-8. Format of Asynchronous Serial Interface Operation Mode Register
61 (ASIM61) (2/2)
Change of bit 0 from INTSR6n to TXSF6n of 14.3 (3) Asynchronous serial interface transmission status register
6n (ASIF6n), Figure 14-11. Format of Asynchronous Serial Interface Transmission Status Register 60
(ASIF60) and Figure 14-12. Format of Asynchronous Serial Interface Transmission Status Register 61
(ASIF61)
Figure 14-15. Format of Baud Rate Generator Control Register 60 (BRGC60)
Figure 14-16. Format of Baud Rate Generator Control Register 61 (BRGC61)
Change of Caution in 14.3 (6) Asynchronous serial interface control register 6n (ASICL6n)
Change of Caution 1, 2 and 4 and Addition of Caution 6 in Figure 14-17. Format of Asynchronous Serial
Interface Control Register 60 (ASICL60) (2/2)
Change of Caution 1, 2 and 4 and Addition of Caution 6 in Figure 14-18. Format of Asynchronous Serial
Interface Control Register 61 (ASICL61) (2/2)
Change of Caution in 14.4.1 (1) Register used
Change of explanation in 14.4.2 (2) (c) Normal transmission
Change of bit 0 from INTSR6n to TXSF6n of 14.4.2 (d) Continuous transmission
Change of bit 0 from INTSR6n to TXSF6n of Figure 14-24. Example of Continuous Transmission Processing
Flow
Change of bit 0 from INTSR6n to TXSF6n of Figure 14-25. Timing of Starting Continuous Transmission
Change of bit 0 from INTSR6n to TXSF6n of Figure 14-26. Timing of Ending Continuous Transmission
Change of Caution 1 in 14.4.2 (2) (e) Normal reception
Change of explanation in 14.4.2 (2) (h) SBF transmission
Change of explanation in 14.4.3 (2) (a) Baud rate
Table 14-4. Set Data of Baud Rate Generator
Change of Table 14-5. Maximum/Minimum Permissible Baud Rate Error
Change of Table 15-1. Configuration of Serial Interfaces CSI10 and CSI11
Figure 15-1. Block Diagram of Serial Interface CSI10
Figure 15-2. Block Diagram of Serial Interface CSI11
Change of Note 2 and 5 in Figure 15-3. Format of Serial Operation Mode Register 10 (CSIM10)
Change of Note 2 and 5 in Figure 15-4. Format of Serial Operation Mode Register 11 (CSIM11)
Change of Caution 2 in Figure 15-5. Format of Serial Clock Selection Register 10 (CSIC10)
Change of Caution 2 in Figure 15-6. Format of Serial Clock Selection Register 11 (CSIC11)
Change of note 1 in 15.4.1 (1) (a) • Serial operation mode register 10 (CSIM10) and • Serial operation mode
register 11 (CSIM11)
Addition of Remark 1 in Figure 15-11. Timing of Clock/Data Phase
APPENDIX D REVISION HISTORY
User’s Manual U17554EJ4V0UD
Description
(4/9)
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