UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 321

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(2) Asynchronous serial interface reception error status register 6n (ASIS6n)
Address: FF53H After reset: 00H R
ASIS60
Cautions 1.
Symbol
This register indicates an error status on completion of reception by serial interfaces UART60 and UART61. It
includes three error flag bits (PE6n, FE6n, OVE6n).
This register is read-only by an 8-bit memory manipulation instruction.
Reset signal generation, or clearing bit 7 (POWER6n) or bit 5 (RXE6n) of ASIM6n to 0 clears this register to 00H.
00H is read when this register is read. If a reception error occurs, read ASIS6n and then read receive buffer
register 6n (RXB6n) to clear the error flag.
Figure 14-9. Format of Asynchronous Serial Interface Reception Error Status Register 60 (ASIS60)
2.
3.
4.
OVE60
PE60
FE60
The operation of the PE60 bit differs depending on the set values of the PS610 and PS600
bits of asynchronous serial interface operation mode register 60 (ASIM60).
The first bit of the receive data is checked as the stop bit, regardless of the number of stop
bits.
If an overrun error occurs, the next receive data is not written to receive buffer register 60
(RXB60) but discarded.
If data is read from ASIS60, a wait cycle is generated. Do not read data from ASIS60 when the
CPU is operating on the subsystem clock and the high-speed system clock is stopped. For
details, see CHAPTER 31 CAUTIONS FOR WAIT.
7
0
0
1
0
1
0
1
If POWER60 = 0 and RXE60 = 0, or if ASIS60 register is read
If the parity of transmit data does not match the parity bit on completion of reception
If POWER60 = 0 and RXE60 = 0, or if ASIS60 register is read
If the stop bit is not detected on completion of reception
If POWER60 = 0 and RXE60 = 0, or if ASIS60 register is read
If receive data is set to the RXB60 register and the next reception operation is completed before the
data is read.
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
6
0
5
0
User’s Manual U17554EJ4V0UD
Status flag indicating framing error
Status flag indicating overrun error
Status flag indicating parity error
4
0
3
0
PE60
2
FE60
1
OVE60
0
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