UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 722

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

D.2 Revision History of Preceding Editions
722
3rd
Edition
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
• Change of the explanation
• Addition of Table 5-3. Setting Functions of P80/ANI0 to P87/ANI7 Pins and Caution
• Change of the explanation
• Addition of Table 5-4. Setting Functions of P90/ANI8 to P93/ANI11 Pins and Caution
Addition of PG-FPL3 in Documents Related to Flash Memory Programming
Addition of Caution 1 to 4 to 1.4 Pin Configuration (Top View)
Change of 10-bit A/D converter number for 78K0/FC2 in 1.5.1 78K0/Fx2 product lineup
Change of EV
Change of REGC in Table 2-3. Non-port pins (2/2)
Change of 2.2.15 REGC
Change of Figure 3-1. Memory Map (
Addition of Note 3 and 4 and Remark in Figure 3-1. Memory Map (
Change of Figure 3-2. Memory Map (
Addition of Note 3 and 4 and Remark in Figure 3-2. Memory Map (
Change of Figure 3-3. Memory Map (
Addition of Note 3 and 4 and Remark in Figure 3-3. Memory Map (
Change of Figure 3-4. Memory Map (
Addition of Note 3 and 4 and Remark in Figure 3-4. Memory Map (
Addition of Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory
Addition of (5) On-chip debug security ID setting area in 3.1.1 Internal program memory space
Addition of Caution 4 in 3.1.2 Bank area (
Addition of Note 1 in Table 3-8. Special Function Register List (4/6)
Change of Note in Table 3-8. Special Function Register List (6/6)
Addition of CHAPTER 4 MEMORY BANK SELECT FUNCTION (
Change of EV
Addition of Caution in 5.2.1 Port 0
Addition of Caution in 5.2.2 Port 1
Addition of Caution 1 in 5.2.3 Port 3
Change of the explanation in 5.2.6 Port 6
5.2.8 Port 8
5.2.9 Port 9
Addition of Caution 1 in 5.2.10 Port 12
Change of Figure 5-17. Block Diagram of P120
Change of Figure 5-18. Block Diagram of P121 to P124
Addition of ADPC in 5.3 Registers Controlling Port Function
Addition of (4) A/D port configuration register (ADPC) in 5.3 Registers Controlling Port Function
Addition of 5.5 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)
Change of Caution 1 and Addition of Caution 3 in 6.3 (4) Main OSC control register (MOC)
Change of Caution 2 and 3 in 6.3 (5) Clock operation mode select register (OSCCTL)
Addition of the explanation in 6.4.1 X1 oscillator and 6.4.2 XT1 oscillator
Addition of (b) External clock in Figure 6-9. Example of External Circuit of X1 Oscillator and Figure 6-10.
Example of External Circuit of XT1 Oscillator
DD
DD
and V
and V
DD
DD
in Table 2-1. Pin I/O Buffer Power Supplies
in Table 5-1. Pin I/O Buffer Power Supplies
APPENDIX D REVISION HISTORY
User’s Manual U17554EJ4V0UD
μ
μ
μ
μ
PD78F0887)
PD78F0888)
PD78F0889)
PD78F0890)
μ
PD78F0889 and 78F0890 only)
Description
μ
PD78F0889, 78F0890 ONLY)
μ
μ
μ
μ
PD78F0887)
PD78F0888)
PD78F0889)
PD78F0890)
(1/9)