UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 154

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(1) CPU operating with high-speed system clock (C) after reset release (A)
(2) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(3) CPU operating with subsystem clock (D) after reset release (A)
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(A) → (B)
Status Transition
(A) → (B) → (C) (X1 clock: less than 10 MHz)
(A) → (B) → (C) (external main clock: less than 10
MHz)
(A) → (B) → (C) (X1 clock: 10 MHz or more)
(A) → (B) → (C) (external main clock: 10 MHz or
more)
Status Transition
(A) → (B) → (D) (XT1 clock)
(A) → (B) → (D) (external subsystem clock)
Table 6-4 shows transition of the CPU clock and examples of setting the SFR registers.
Remarks 1. (A) to (I) in Table 6-4 correspond to (A) to (I) in Figure 6-14.
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
Status Transition
MSTOP:
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
CSS:
Table 6-4. CPU Clock Transition and SFR Register Setting Examples (1/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
Bit 7 of the main OSC control register (MOC)
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 4 of the processor clock control register (PCC)
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17554EJ4V0UD
SFR registers do not have to be set (default status after reset release).
AMPH
0
0
1
1
EXCLKS
0
1
EXCLK
0
1
0
1
OSCSEL
OSCSELS
1
1
1
1
SFR Register Setting
1
1
MSTOP
0
0
0
0
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
Must not be
Must not be
checked
checked
Must be
Must be
Register
checked
checked
OSTC
XSEL
1
1
1
1
CSS
1
1
MCM0
1
1
1
1