UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 698

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Caution When Value is Φ
Remark F
698
CAN
Peripheral
Hardware
F
F
VPCLK
VPSTB
CANCLK
Global Reg.
CANmodule
Reg.
C0RGPT
C0LIPT
C0TGPT
C0LOPT
Message Buf.
Message Buf.
Message Buf.
:
:
: AFCAN macro frequency
Table 31-2 RAM Access That Generate Wait and Number of CPU Wait Clocks
Register
VPCLK frequency
VPSTB frequency
CANMOD
Read/Write
Read
Write(8 bit)
Write(16 bit)
(CAN module system clock) ≥ 2 MHz.
Access
CHAPTER 31 CAUTIONS FOR WAIT
User’s Manual U17554EJ4V0UD
number of wait clocks
MIN.
1
2
2
1
MAX.
14
17
11
1
synchronizaition of NPB signals with VPCLK
<Calculating number of wait clocks>
MIN. ROUNDUP[(1/F
MAX. ROUNDUP[(1/F
Synchronization of NPB signals with VPCLK
RAM access delay (1 RAM - RD access)
<Calculating number of wait clocks>
MIN. ROUNDUP[(1/F
MAX. ROUNDUP[(1/F
synchronization of NPB signals with VPCLK
RAM access delay (1RAM - RD + 1RAM - WR
access)
<Calculating number of wait clocks>
MIN. ROUNDUP[(1/F
MAX. ROUNDUP[(1/F
synchronization of NPB signals with VPCLK
RAM access delay (1 RAM - WR access)
<Calculating number of wait clocks>
MIN. ROUNDUP[(1/F
MAX. ROUNDUP[(1/F
Cause
VPCLK
CANCLK
CANCLK
CANCLK
VPCLK
CANCLK
CANCLK
CANCLK
) × 1/(1/F
) × 2/(1/F
) × 3/(1/F
) × 4/(1/F
) × 2/(1/F
) × 4/(1/F
) × 5/(1/F
) × 3/(1/F
VPSTB
VPSTB
VPSTB
VPSTB
VPSTB
VPSTB
VPSTB
VPSTB
)]
)]
)]
)]
)]
)]
)]
)]