UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 197

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

f
f
PRS
PRS
Note
/2
/2
TI000/P00
(TI001/P05)
TI002/P31
(TI003/P131)
f
Cautions 1. CR00n cannot be rewritten during TM0n operation.
Remarks 1.
2
8
PRS
(f
(f
PRS
PRS
(f
PRS
/2
/2
Frequencies and pin names without parentheses are for 16-bit timer/event counter 00 and 02, and those in
parentheses are for 16-bit timer/event counter 01 and 03.
4
6
)
)
)
Note
Note
Note
Note
2.
2. In the PPG output operation, change the pulse width (rewrite CR01n) during TM0n operation
CR00n capture value
CR01n capture value
Noise
eliminator
TM0n count value
using the following procedure.
<1> Disable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 0)
<2> Disable the INTTM01n interrupt (TMMK01n = 1)
<3> Rewrite CR01n
<4> Wait for 1 cycle of the TM0n count clock
<5> Enable the timer output inversion operation by match of TM0n and CR01n (TOC0n4 = 1)
<6> Clear the interrupt request flag of INTTM01n (TMIF01n = 0)
<7> Enable the INTTM01n interrupt (TMMK01n = 0)
0000H ≤ M < N ≤ FFFFH
n = 0 to 3
f
PRS
Count clock
TO0n
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03
Figure 7-32. Configuration Diagram of PPG Output
Figure 7-33. PPG Output Operation Timing
N
Clear
0000H
t
Pulse width: (M + 1)
16-bit timer capture/compare
0001H
16-bit timer capture/compare
User’s Manual U17554EJ4V0UD
16-bit timer counter 0n
register 00n (CR00n)
register 01n (CR01n)
1 cycle: (N + 1)
(TM0n)
M
1
N
M
t
M
t
N
1
circuit
Clear
N
Clear
0000H 0001H
TO00/TI010/P01
(TO01/TI011/P06)
TO02/TI012/P32
(TO03/TI013/P132)
197
Note