UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 364

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
(3) Port mode registers 0, 1 and 7 (PM0, PM1, PM7)
364
Address: FF20H After reset: FFH R/W
Address: FF21H After reset: FFH R/W
Address: FF2CH After reset: FFH R/W
Symbol
Symbol
Symbol
PM0
PM1
PM7
These registers set port 0, 1 and 7 input/output in 1-bit units.
When using P10/SCK10 and P76/SCK11 as the clock output pins of the serial interface, clear PM10 and PM76,
and the output latches of P10 and P76 to 1.
When using P12/SO10 and P74/SO11 as the data output pins of the serial interface, clear PM12, PM74, P12 and
P74 to 0.
When using P10/SCK10/TxD61 and P76/SCK11 as the clock input pins of the serial interface, P11/SI10/RxD61
and P75/SI11 as the data input pins, and P05/SSI11/TI001 as the chip select input pin, set PM10, PM76, PM11,
PM75 and PM05 to 1. At this time, the output latches of P10, P76, P11, P75 and P05 may be 0 or 1.
PM0, PM1 and PM7 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
PM0n
PM17
PM1n
PM7n
7
1
0
1
7
0
1
7
1
0
1
Output mode (Output buffer on)
Input mode (Output buffer off)
Output mode (Output buffer on)
Input mode (Output buffer off)
Output mode (Output buffer on)
Input mode (Output buffer off)
PM06
PM16
PM76
CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11
Figure 15-7. Format of Port Mode Register 0 (PM0)
6
Figure 15-8. Format of Port Mode Register 1 (PM1)
6
Figure 15-9. Format of Port Mode Register 7 (PM7)
6
PM05
PM15
PM75
5
5
5
User’s Manual U17554EJ4V0UD
P0n pin I/O mode selection (n = 0, 1, 5, 6)
P1n pin I/O mode selection (n = 0 to 7)
P7n pin I/O mode selection (n = 0 to 6)
PM14
PM74
4
1
4
4
PM13
PM73
3
1
3
3
PM12
PM72
2
1
2
2
PM11
PM71
PM01
1
1
1
PM00
PM10
PM70
0
0
0

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