UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 574

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(2) In 2.7 V / 1.59V POC mode (option byte: LVISTART = 1)
574
oscillation clock (f
(when X1 oscillation
Internal reset signal
Internal high-speed
system clock (f
Notes 1.
Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
Remark V
V
V
DDPOC
Supply voltage
POC
High-speed
is selected)
= 1.59 V (TYP.)
= 2.7 V (TYP.)
1.8 V
2.
CPU
(V
RH
XH
Note 1
V
DD
0 V
LVI
)
)
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
V
2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
)
Operation
The operation guaranteed range is 1.8 V ≤ V
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
LVI
POC
LOW-VOLTAGE DETECTOR).
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
stops
: LVI detection voltage
: POC detection voltage
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Normal operation
specified by software.
Starting oscillation is
and Low-Voltage Detector (2/2)
Note 2
User’s Manual U17554EJ4V0UD
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
used for interrupt
Set LVI to be
DD
oscillation clock)
(internal high-speed
Normal operation
≤ 5.5 V. To make the state at lower than 1.8 V reset
specified by software.
Starting oscillation is
Note 2
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
Note 2
Operation stops