UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 727

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

3rd
Edition
• Change of Figure 18-1 and Caution 2
Addition of Note in Table 18-1. Operating Statuses in HALT Mode (2/2)
• Change of Figure 18-5
• Addition of Note1 and 2
Addition of Note 2 in Figure 16-40. Message Buffer Redefinition
Addition of Remark in Figure 16-44. Transmission via Interrupt (Using C0LOPT Register)
Addition of Remark in Figure 16-45. Transmission via Interrupt (Using C0TGPT Register)
Addition of Remark in Figure 16-46. Transmission via Software Polling
Addition of Note in Figure 16-47. Transmission Abort Processing (Except Normal Operation Mode with ABT)
Addition of Note in Figure 16-48. Transmission Abort Processing Except for ABT Transmission (Normal
Operation Mode with ABT)
Change of Figure 16-51. Reception via Interrupt (Using C0LIPT Register) and addition of Remark
Change of Figure 16-52. Reception via Interrupt (Using C0RGPT Register) and addition of Remark
Change of Figure 16-53. Reception via Software Polling and addition of Remark
Change of Figure 16-54. Setting CAN Sleep Mode/Stop Mode
Change of Figure 16-55. Clear CAN Sleep/Stop Mode
Addition of Note, Caution and Remark in Figure 16-56. Bus-Off Recovery (Except Normal Operation Mode with
ABT)
Addition of Note, Caution and Remark in Figure 16-57. Bus-Off Recovery (Normal Operation Mode with ABT)
Change of Figure 16-61. Setting CPU Standby (from CAN Sleep Mode) and addition of Caution
Change of Figure 16-62. Setting CPU Standby (from CAN Stop Mode)
Change of explanation in 17.1 (1) Maskable interrupts
Change of explanation in 17.2 Interrupt Sources and Configuration
Addition of Note 3 in Table 17-1. Interrupt Source List (2/2)
Addition of Note 3 in Table 17-2. Flags Corresponding to Interrupt Request Sources
Change of Caution 3 in 18.1.1 (2) STOP mode
Figure 18-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Change of explanation and Caution 3 in 18.1.2 (2) Oscillation stabilization time select register (OSTS)
Change of Table 18-1. Operating Statuses in HALT Mode
Change of Figure 18-4. HALT Mode Release by Reset
Change and addition of Note in Table 18-3. Operating Statuses in STOP Mode
Change of Caution 4 in Table 18-3. Operating Statuses in STOP Mode
Figure 18-5. Operation Timing When STOP Mode Is Released
Change of Figure 18-6. STOP Mode Release by Interrupt Request Generation
Change of 18.2.2 (2) (b) Release by reset signal generation and Figure 18-7. STOP Mode Release by Reset
Change of explanation in CHAPTER 19 RESET FUNCTION
Change of Figure 19-2. Timing of Reset by RESET Input and Figure 19-3. Timing of Reset Due to Watchdog
Timer Overflow
Change of Figure 19-4. Timing of Reset in STOP Mode by RESET Input
Change of Table 19-1. Operation Statuses During Reset Period
Addition of Note 1 in Table 19-2. Hardware Statuses After Reset Acknowledgment (2/3)
Addition of Note 1 and change of Note 2 in Table 19-2. Hardware Statuses After Reset Acknowledgment (3/3)
Change of explanation in 21.1 Functions of Power-on-Clear Circuit
Change of 21.3 Operation of Power-on-Clear Circuit
APPENDIX D REVISION HISTORY
User’s Manual U17554EJ4V0UD
Description
(6/9)
727