UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 318

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

318
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE60) of asynchronous serial
Cautions 1.
Figure 14-7. Format of Asynchronous Serial Interface Operation Mode Register 60 (ASIM60) (2/2)
interface reception error status register 60 (ASIS60) is not set and the error interrupt does not occur.
2.
3.
4.
5.
6.
7.
8.
9.
ISRM60
PS610
CL60
SL60
To start the transmission, set POWER60 to 1 and then set TXE60 to 1. To stop the
transmission, clear TXE60 to 0, and then clear POWER60 to 0.
To start the reception, set POWER60 to 1 and then set RXE60 to 1. To stop the reception,
clear RXE60 to 0, and then clear POWER60 to 0.
Set POWER60 to 1 and then set RXE60 to 1 while a high level is input to the RxD60 pins. If
POWER60 is set to 1 and RXE60 is set to 1 while a low level is input, reception is started.
TXE60 and RXE60 are synchronized by the base clock (f
transmission or reception again, set TXE60 or RXE60 to 1 at least two clocks of the base
clock after TXE60 or RXE60 has been cleared to 0. If TXE60 or RXE60 is set within two clocks
of the base clock, the transmission circuit or reception circuit may not be initialized.
Set transmit data to TXB60 at least one base clock (f
Clear the TXE60 and RXE60 bits to 0 before rewriting the PS610, PS600, and CL60 bits.
Fix the PS610 and PS600 bits to 0 when used in LIN communication operation.
Clear TXE60 to 0 before rewriting the SL60 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL60 bit.
Make sure that RXE60 = 0 when rewriting the ISRM60 bit.
0
0
1
1
0
1
0
1
0
1
Character length of data = 7 bits
Character length of data = 8 bits
Number of stop bits = 1
Number of stop bits = 2
“INTSRE60” occurs in case of error (at this time, INTSR60 does not occur).
“INTSR60” occurs in case of error (at this time, INTSRE60 does not occur).
PS600
CHAPTER 14 SERIAL INTERFACES UART60 AND UART61
0
1
0
1
Enables/disables occurrence of reception completion interrupt in case of error
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
User’s Manual U17554EJ4V0UD
Transmission operation
Specifies character length of transmit/receive data
Specifies number of stop bits of transmit data
XCLK6
) after setting TXE60 = 1.
Reception without parity
Reception as 0 parity
Judges as odd parity.
Judges as even parity.
XCLK6
) set by CKSR60. To enable
Reception operation
Note