UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 218

8BIT MCU, 128K FLASH, 7K RAM, LQFP

UPD78F0890GK(A)-GAJ-AX

Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet

Specifications of UPD78F0890GK(A)-GAJ-AX

Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
7.6 Cautions for 16-Bit Timer/Event Counters 00 to 03
(1) Restrictions for each channel of 16-bit timer/event counter 0n
(2) Timer start errors
(3) Setting of CR00n and CR01n (clear & start mode entered upon a match between TM0n and CR00n)
218
As interval timer
As square-wave output
As external event counter
As clear & start mode entered by
TI00n pin valid edge input
As free-running timer
As PPG output
As one-shot pulse output
As pulse width measurement
Table 7-5 shows the restrictions for each channel.
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because counting TM0n is started asynchronously to the count pulse.
Set a value other than 0000H to CR00n and CR01n (TM0n cannot count one pulse when it is used as an external
event counter).
Remark n = 0 to 3
Operation
Table 7-5. Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n
TM0n count value
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 03
Count pulse
Using timer output (TO0n) is prohibited when detection of the valid edge of the TI01n pin is
used. (TOC0n = 00H)
0000H ≤ CP01n < CR00n ≤ FFFFH
Setting the same value to CR00n and CP01n is prohibited.
Using timer output (TO0n) is prohibited (TOC0n = 00H)
Figure 7-55. Start Timing of TM0n Count
Timer start
User’s Manual U17554EJ4V0UD
0000H
0001H
0002H
Restriction
0003H
0004H

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