UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 571
UPD78F0890GK(A)-GAJ-AX
Manufacturer Part Number
UPD78F0890GK(A)-GAJ-AX
Description
8BIT MCU, 128K FLASH, 7K RAM, LQFP
Manufacturer
NEC
Datasheet
1.UPD78F0890GKA-GAJ-AX.pdf
(732 pages)
Specifications of UPD78F0890GK(A)-GAJ-AX
Controller Family/series
UPD78F
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
10
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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21.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the following functions.
• Generates internal reset signal at power on.
• Compares supply voltage (V
In the 1.59 V POC mode (option byte: LVISTART = 0), the reset signal is released when the supply voltage
(V
In the 2.7 V/1.59 V POC mode (option byte: LVISTART = 1), the reset signal is released when the supply
voltage (V
when V
Caution If an internal reset signal is generated in the POC circuit, the reset control flag register (RESF)
Remark The 78K0/FE2 incorporates multiple hardware functions that generate an internal reset signal. A flag
DD
) exceeds 1.59 V ±0.15 V.
DD
DD
< V
is cleared to 00H.
that indicates the reset cause is located in the reset control flag register (RESF) for when an internal
reset signal is generated by the watchdog timer (WDT) or low-voltage-detector (LVI). RESF is not
cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI.
For details of RESF, see CHAPTER 19 RESET FUNCTION.
) exceeds 2.7 V ±0.2 V.
POC
.
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
DD
) and detection voltage (V
User’s Manual U17554EJ4V0UD
POC
= 1.59 V ±0.15 V), generates internal reset signal
571
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