UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 402

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

402
(b) Resynchronization
Synchronization is established again if a level change is detected on the bus during reception (only if a
recessive level was sampled previously).
- The phase error of the edge is given by the relative position of the detected edge and sync segment.
- The sample point of the data of the receiving node moves relatively due to the “discrepancy” in baud
<Sign of phase error>
rate between the transmitting node and receiving node.
0: If the edge is within the sync segment
Positive: If the edge is before the sample point (phase error)
Negative: If the edge is after the sample point (phase error)
If phase error is positive: Phase segment 1 is longer by specified SJW.
If phase error is negative: Phase segment 2 is shorter by specified SJW.
Bit timing
CAN bus
CAN bus
Bit timing
Sync
segment
Sync
segment
Figure 16-21. Resynchronization
CHAPTER 16 CAN CONTROLLER
Prop
segment
Prop
segment
User’s Manual U17554EJ4V0UD
If phase error is positve
If phase error is negative
Phase segment 1
Phase segment 1
Sample point
Phase
segment 2
Sample point
Data bit time(DBT)
Phase
segment 2