UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 155

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
Status Transition
(B) → (C) (X1 clock: less than 10 MHz)
(B) → (C) (external main clock: less than 10 MHz)
(B) → (C) (X1 clock: 10 MHz or more)
(B) → (C) (external main clock: 10 MHz or more)
Status Transition
(B) → (D) (XT1 clock)
(B) → (D) (external subsystem clock)
Remarks 1. (A) to (I) in Table 6-4 correspond to (A) to (I) in Figure 6-14.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
MSTOP:
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
CSS:
Table 6-4. CPU Clock Transition and SFR Register Setting Examples (2/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bit 4 of the processor clock control register (PCC)
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17554EJ4V0UD
Unnecessary if these registers
AMPH
0
0
1
1
EXCLKS
0
1
are already set
Unnecessary if the CPU is operating
EXCLK
0
1
0
1
with the subsystem clock
OSCSEL
OSCSELS
1
1
1
1
1
1
MSTOP
with the high-speed
Unnecessary if the
CPU is operating
0
0
0
0
system clock
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
Must not be
Must not be
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Unnecessary if this
register is already
XSEL
1
1
1
1
↑
set
CSS
1
1
MCM0
1
1
1
1
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