UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 573

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(1) In 1.59 V POC mode (option byte: LVISTART = 0)
oscillation clock (f
(when X1 oscillation
Internal reset signal
Internal high-speed
V
system clock (f
POC
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
Remark V
= 1.59 V (TYP.)
High-speed
is selected)
Supply voltage
1.8 V
CPU
2.
3.
4.
RH
XH
(V
Note 1
V
)
)
0 V
Operation
LVI
DD
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
LOW-VOLTAGE DETECTOR).
V
)
The operation guaranteed range is 1.8 V ≤ V
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
If the voltage rises to 1.8 V at a rate slower than 0.5 V/ms (MIN.) on power application, input a low level
to the RESET pin after power application and before the voltage reaches 1.8 V, or set the 2.7 V/1.59 V
POC mode by using an option byte (LVISTART = 1).
The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
LVI
POC
stops
: LVI detection voltage
: POC detection voltage
specified by software.
Wait for voltage
(1.93 to 5.39 ms)
Starting oscillation is
0.5 V/ms (MIN.)
Note 3
stabilization
Reset processing (11 to 45 s)
Note 2
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
and Low-Voltage Detector (1/2)
Note 4
User’s Manual U17554EJ4V0UD
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
used for interrupt
Reset processing (11 to 45 s)
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
DD
≤ 5.5 V. To make the state at lower than 1.8 V reset
Note 4
Reset period
(oscillation
stop)
(1.93 to 5.39 ms)
Note 3
Wait for voltage
specified by software.
Starting oscillation is
stabilization
Reset processing (11 to 45 s)
used for reset
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
Note 4
Operation stops
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