UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 597

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

23.2 Format of Option Byte
Address: 0080H/1080H
The format of the option byte is shown below.
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is
Remarks 1.
boot swap operation.
2.
2. The watchdog timer continues its operation during self-programming and EEPROM
3. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
4. Be sure to clear bit 7 to 0.
WINDOW1
LSROSC
WDTON
WDCS2
prohibited.
emulation of the flash memory.
delayed. Set the overflow time and window size taking this delay into consideration.
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of
the internal oscillator mode register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
f
( ): f
RL
7
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
1
: Internal low-speed oscillation clock frequency
RL
Note
= 264 kHz (MAX.)
Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
Can be stopped by software (stopped when 1 is written to bit 0 (LSRSTOP) of RCM register)
Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
WINDOW1
WINDOW0
WDCS1
6
0
1
0
1
0
0
1
1
0
0
1
1
Figure 23-1. Format of Option Byte (1/2)
25%
50%
75%
100%
WINDOW0
Operation control of watchdog timer counter/illegal access detection
WDCS0
CHAPTER 23 OPTION BYTE
5
0
1
0
1
0
1
0
1
User’s Manual U17554EJ4V0UD
2
2
2
2
2
2
2
2
10
11
12
13
14
15
16
17
Internal low-speed oscillator operation
WDTON
/f
/f
/f
/f
/f
/f
/f
/f
RL
RL
RL
RL
RL
RL
RL
RL
During processing, the interrupt acknowledge time is
4
(3.88 ms)
(7.76 ms)
(15.52 ms)
(31.03 ms)
(62.06 ms)
(124.12 ms)
(248.24 ms)
(496.48 ms)
Watchdog timer window open period
WDCS2
3
Watchdog timer overflow time
WDCS1
2
WDCS0
1
LSROSC
0
597