UPD78F0890GK(A)-GAJ-AX NEC, UPD78F0890GK(A)-GAJ-AX Datasheet - Page 471

• Manufacturer Part Number: UPD78F0890GK(A)-GAJ-AX
• Description: 8BIT MCU, 128K FLASH, 7K RAM, LQFP
• Manufacturer: NEC

Specifications of UPD78F0890GK(A)-GAJ-AX

• Controller Family/series: UPD78F
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 10
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

16.10.4 Transmission abort process
(1) Transmission abort process except for in normal operation mode with automatic block transmission
(2) Transmission abort process except for ABT transmission in normal operation mode with automatic
(ABT)
The user can clear the TRQ bit of the C0MCTRLm register to 0 to abort a transmission request. The TRQ bit
will be cleared immediately if the abort was successful. Whether the transmission was successfully aborted
or not can be checked using the TSTAT bit of the C0CTRL register and the C0TGPT register, which indicate
the transmission status on the CAN bus (for details, refer to the processing in Figure 16-47).
block transmission (ABT)
The user can clear the ABTTRG bit of the C0GMABT register to 0 to abort a transmission request. After
checking the ABTTRG bit of the C0GMABT register = 0, clear the TRQ bit of the C0MCTRLm register to 0.
The TRQ bit will be cleared immediately if the abort was successful.
successfully aborted or not can be checked using the TSTAT bit of the C0CTRL register and the C0TGPT
register, which indicate the transmission status on the CAN bus (for details, refer to the processing in Figure
16-48).
Cautions 1.
Remark m = 0 to 15
2.
3.
4.
5.
6.
7.
8.
Set the ABTCLR bit to 1 while the ABTTRG bit is cleared to 0 in order to resume ABT
operation at buffer No.0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to
1, the subsequent operation is not guaranteed.
If the automatic block transmission engine is cleared by setting the ABTCLR bit to 1,
the ABTCLR bit is automatically cleared immediately after the processing of the
clearing request is completed.
Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in the
initialization mode, the proper operation is not guaranteed after the mode is changed
from the initialization mode to the ABT mode.
Do not set TRQ bit of the ABT message buffers to 1 by software in the normal
operation mode with ABT. Otherwise, the operation is not guaranteed.
The C0GMABTD register is used to set the delay time that is inserted in the period
from completion of the preceding ABT message to setting of the TRQ bit for the next
ABT message when the transmission requests are set in the order of message
numbers for each message for ABT that is successively transmitted in the ABT
mode. The timing at which the messages are actually transmitted onto the CAN bus
varies depending on the status of transmission from other stations and the status of
the setting of the transmission request for messages other than the ABT messages
(message buffer 8 to 15).
If a transmission request is made for a message other than an ABT message and if
no delay time is inserted in the interval in which transmission requests for ABT are
automatically set (C0GMABTD = 00H), messages other than ABT messages may be
transmitted not depending on the priority of the ABT message.
Do not clear the RDY bit to 0 when ABTTRG = 1.
If a message is received from another node while normal operation mode with ABT is
active, the TX-message from the ABT-area may be transmitted with delay of one
frame although CnGMABTD register was set up with 00H.
CHAPTER 16 CAN CONTROLLER
User’s Manual U17554EJ4V0UD
Whether the transmission was
471