EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 108

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

6–8
Table 6–3. Selectable I/O Drivers for On-Chip Series Termination with and Without Calibration Setting (Part 2 of 2)
On-Chip Series Termination with Calibration
Cyclone III Device Handbook, Volume 1
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
I/O Standard
The Cyclone III device family supports on-chip series termination with calibration in
all banks. The on-chip series termination calibration circuit compares the total
impedance of the I/O buffer to the external 25-Ω ±1% or 50-Ω ±1% resistors
connected to the RUP and RDN pins, and dynamically adjusts the I/O buffer
impedance until they match (as shown in
The R
the I/O buffer.
Figure 6–2. Cyclone III Device Family On-Chip Series Termination with Calibration
OCT with calibration is achieved using the OCT calibration block circuitry. There is
one OCT calibration block in banks 2, 4, 5, and 7. Each calibration block supports each
side of the I/O banks. Because there are two I/O banks sharing the same calibration
block, both banks must have the same V
two related banks have different V
resides can enable OCT calibration.
On-Chip Series Termination with Calibration
S
shown in
Row I/O
50
25
50
25
50
25
50
—
Setting, in ohms (Ω)
Figure 6–2
Driver Series Termination
Cyclone III Device Family
Column I/O
is the intrinsic impedance of the transistors that make up
50
25
50
25
50
25
50
25
V
GND
CCIO
CCIO
R
R
S
S
s, only the bank in which the calibration block
CCIO
Figure
On-Chip Series Termination Without Calibration
Chapter 6: I/O Features in the Cyclone III Device Family
if both banks enable OCT calibration. If
Z
6–2).
O
Row I/O
50
25
50
25
50
25
50
—
Setting, in ohms (Ω)
Receiving
© December 2009 Altera Corporation
Device
Column I/O
50
25
50
25
50
25
50
25
OCT Support