EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 133

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Figure 7–4. BLVDS Topology with Cyclone III Device Family Transmitters and Receivers
© December 2009
100 kΩ
100 kΩ
GND
f
f
R
1
T
Altera Corporation
V
CC
Figure 7–4
pairs.
The BLVDS I/O standard is supported on all I/O banks of the Cyclone III device
family. The BLVDS transmitter uses two single-ended output buffers with the second
output buffer programmed as inverted, while the BLVDS receiver uses a true LVDS
input buffer. The transmitter and receiver share the same pins. An output-enabled
(OE) signal is required to tristate the output buffers when the LVDS input buffer
receives a signal.
For more information about BLVDS I/O features and electrical specifications, refer to
the
Handbook and the
chapters.
For more information and design examples about implementing the BLVDS interfaces
in the Cyclone III device family, refer to
Cyclone III, Stratix III and Stratix IV
Designing with BLVDS
The BLVDS bidirectional communication requires termination at both ends of the bus
in BLVDS. The termination resistor (R
which in turn depends on the loading on the bus. Increasing the load decreases the
bus differential impedance. With termination at both ends of the bus, termination is
not required between the two signals at the input buffer. A single series resistor (R
required at the output buffer to match the output buffer impedance to the
transmission line impedance. However, this series resistor affects the voltage swing at
the input buffer. The maximum data rate achievable depends on many factors.
Altera recommends that you perform simulation using the IBIS model while
considering factors such as bus loading, termination values, and output and input
buffer location on the bus to ensure that the required performance is achieved.
50 Ω
50
Cyclone III Device I/O Features
Ω
Output
Data
shows a typical BLVDS topology with multiple transmitter and receiver
Input
Data
Cyclone III Device Data Sheet
50 Ω
50 Ω
Output
Data
chapter in volume 1 of the Cyclone III Device
Devices.
Input
Data
T
) must match the bus differential impedance,
AN 522: Implementing Bus LVDS Interface in
50 Ω
50 Ω
and
Output
Data
Cyclone III LS Device Data Sheet
Cyclone III Device Handbook, Volume 1
Input
Data
50 Ω
50 Ω
V
CC
100 kΩ
100 k
GND
R
T
Ω
S
) is
7–9