EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 211

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
Altera Corporation
Figure 9–25. JTAG Configuration of a Single Device Using a Download Cable (1.5-V or 1.8-V V
Powering the JTAG Pins)
Notes to
(1) Connect these pull-up resistors to the V
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a
(3) In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming;
(4) The nCE must be connected to GND or driven low for successful JTAG configuration.
(5) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(6) Power up the V
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration upon completion. At
the end of configuration, the software checks the state of CONF_DONE through the
JTAG port. When the Quartus II software generates a .jam for a multi-device chain, it
contains instructions to have all devices in the chain initialize at the same time. If
CONF_DONE is not high, the Quartus II software indicates that configuration has
failed. If CONF_DONE is high, the software indicates that configuration was successful.
After the configuration bitstream is serially sent using the JTAG TDI port, the TCK
port clocks an additional clock cycle to perform device initialization.
JTAG configuration, connect the nCONFIG pin to logic-high and the MSEL[3..0] pins to ground. In addition, pull
DCLK and DATA[0] either high or low, whichever is convenient on your board.
otherwise it is a no connect.
ByteBlaster II, USB-Blaster, and Ethernet Blaster cables do not support a target supply voltage of 1.2 V. For the target
supply voltage value, refer to the
and
Ethernet Blaster Communications Cable User
Figure
V
CCIO
9–25:
10
(1)
CC
V
kΩ
CCIO
of the ByteBlaster II, USB-Blaster, or Ethernet Blaster cable with supply from V
10
(1)
GND
kΩ
(2)
(2)
(2)
(2)
N.C. (5)
Cyclone III Device Family
ByteBlaster II Download Cable User
nCEO
CONF_DONE
nCONFIG
DATA[0]
DCLK
nCE
nSTATUS
MSEL[3..0]
(4)
CCIO
supply of the bank in which the pin resides.
TDO
TMS
TCK
TDI
Guide.
10
kΩ
V
CCIO
V
CCIO
10
1
kΩ
kΩ
Guide,
GND
Pin 1
USB-Blaster Download Cable User Guide
Cyclone III Device Handbook, Volume 1
10-Pin Male Header (Top View)
GND
Download Cable
V
CCIO
V
IO
(6)
(3)
GND
CCIO
. The
CCIO
9–51