EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 84

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

5–20
Cyclone III Device Handbook, Volume 1
Manual Override
If you are using the automatic switchover, you must switch input clocks with the
manual override feature with the clkswitch input.
Figure 5–16
when controlled by clkswitch. In this case, both clock sources are functional and
inclk0 is selected as the reference clock. A low-to-high transition of the clkswitch
signal starts the switchover sequence. The clkswitch signal must be high for at least
three clock cycles (at least three of the longer clock period if inclk0 and inclk1
have different frequencies). On the falling edge of inclk0, the reference clock of the
counter, muxout, is gated off to prevent any clock glitching. On the falling edge of
inclk1, the reference clock multiplexer switches from inclk0 to inclk1 as the PLL
reference. On the falling edge of inclk1, the reference clock multiplexer switches
from inclk0 to inclk1 as the PLL reference, and the activeclock signal changes
to indicate which clock is currently feeding the PLL.
In this mode, the activeclock signal mirrors the clkswitch signal. As both blocks
are still functional during the manual switch, neither clkbad signals go high.
Because the switchover circuit is positive edge-sensitive, the falling edge of the
clkswitch signal does not cause the circuit to switch back from inclk1 to inclk0.
When the clkswitch signal goes high again, the process repeats. The clkswitch
signal and the automatic switch only works depending on the availability of the clock
that is switched to. If the clock is unavailable, the state machine waits until the clock is
available.
Figure 5–16. Clock Switchover Using the clkswitch Control
Note to
(1) Both inclk0 and inclk1 must be running when the clkswitch signal goes high to start a manual clock
Manual Clock Switchover
Cyclone III device family PLLs support manual switchover, in which the clkswitch
signal controls whether inclk0 or inclk1 is the input clock to the PLL. The
characteristics of a manual switchover is similar to the manual override feature in an
automatic clock switchover, in which the switchover circuit is edge-sensitive. When
the clkswitch signal goes high, the switchover sequence starts. The falling edge of
the clkswitch signal does not cause the circuit to switch back to the previous input
clock.
switchover event.
Figure
5–16:
shows an example of a waveform illustrating the switchover feature
activeclock
clkswitch
clkbad0
clkbad1
muxout
inclk0
inclk1
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
(1)
© December 2009 Altera Corporation
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