EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 232

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

9–72
Table 9–23. Optional Configuration Pins
Cyclone III Device Handbook, Volume 1
CLKUSR
INIT_DONE
DEV_OE
DEV_CLRn
Pin Name
N/A if option is on.
N/A if option is on.
N/A if option is on.
N/A if option is on.
I/O if option is off.
I/O if option is off.
I/O if option is off.
I/O if option is off.
Table 9–23
are not enabled in the Quartus II software, they are available as general-purpose user
I/O pins. Therefore, during configuration, these pins function as user I/O pins and
are tri-stated with weak pull-up resistors.
User Mode
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
lists the optional configuration pins. If these optional configuration pins
open-drain
Pin Type
Output
Input
Input
Input
Quartus II software.
Optional pin that allows you to override all clears on all device
registers. When this pin is driven low, all registers are cleared;
when this pin is driven high, all registers behave as
programmed. This pin is enabled by turning on the Enable
device-wide reset (DEV_CLRn) option in the Quartus II
software.
Optional user-supplied clock input synchronizes the initialization
of one or more devices. This pin is enabled by turning on the
Enable user-supplied start-up clock (CLKUSR) option in the
Status pin used to indicate when the device has initialized and is
in user-mode. When nCONFIG is low and during the beginning
of configuration, the INIT_DONE pin is tri-stated and pulled
high due to an external 10-kΩ pull-up resistor. After the option
bit to enable INIT_DONE is programmed into the device
(during the first frame of configuration data), the INIT_DONE
pin goes low. When initialization is complete, the INIT_DONE
pin is released and pulled high and the device enters user mode.
Thus, the monitoring circuitry must be able to detect a low-to-
high transition. This pin is enabled by turning on the Enable
INIT_DONE output option in the Quartus II software.
The functionality of this pin changes if the Enable OCT_DONE
option is enabled in the Quartus II software. This option
controls whether the INIT_DONE signal is gated by the
OCT_DONE signal, which indicates the Power-Up OCT
calibration is complete. If this option is turned off, the
INIT_DONE signal is not gated by the OCT_DONE signal
Optional pin that allows you to override all tri-states on the
device. When this pin is driven low, all I/O pins are tri-stated;
when this pin is driven high, all I/O pins behave as programmed.
This pin is enabled by turning on the Enable device-wide
output enable (DEV_OE) option in the Quartus II software.
Description
© December 2009 Altera Corporation
Configuration Features