EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 71

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Clock Networks
GCLK Network Power Down
© December 2009
f
Altera Corporation
The inputs to the five clock control blocks on each side must be chosen from among
the following clock sources:
■
■
■
■
From the clock sources listed above, only two clock input pins, two PLL clock
outputs, one DPCLK or CDPCLK pin, and one source from internal logic can drive into
any given clock control block, as shown in
Out of these five inputs to any clock control block, the two clock input pins and two
PLL outputs are dynamically selected to feed a GCLK. The clock control block
supports static selection of the signal from internal logic.
Figure 5–3
the Cyclone III device family periphery.
Figure 5–3. Clock Control Blocks on Each Side of the Cyclone III Device Family
Note to
(1) The left and right sides of the device have two DPCLK pins; the top and bottom of the device have four DPCLK pins.
You can disable the Cyclone III device family GCLK (power down) by using both
static and dynamic approaches. In the static approach, configuration bits are set in the
configuration file generated by the Quartus II software, which automatically disables
unused GCLKs. The dynamic clock enable or disable feature allows internal logic to
control clock enable or disable of the GCLKs in the Cyclone III device family.
When a clock network is disabled, all the logic fed by the clock network is in an
off-state, thereby reducing the overall power consumption of the device. This function
is independent of the PLL and is applied directly on the clock network, as shown in
Figure 5–1 on page
You can set the input clock sources and the clkena signals for the GCLK
multiplexers through the Quartus II software using the ALTCLKCTRL megafunction.
For more information, refer to the
Four clock input pins
Five PLL counter outputs
Two DPCLK pins and two CDPCLK pins from both the left and right sides, and four
DPCLK pins and two CDPCLK pins from both the top and bottom
Five signals from internal logic
Figure
shows a simplified version of the five clock control blocks on each side of
5–3:
5–5.
Clock Input Pins
Internal Logic
PLL Outputs
CDPCLK
DPCLK
ALTCLKCTRL Megafunction User
2 or 4
4
5
2
5
Blocks on Each Side
Five Clock Control
of the Device
Figure 5–1 on page
Control
Clock
Block
5
Cyclone III Device Handbook, Volume 1
GCLK
5–5.
Guide.
(Note 1)
5–7