EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 217

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
© December 2009
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Altera Corporation
Configuring Cyclone III Device Family with Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for in-system
programmability (ISP) purposes. Jam STAPL supports programming or configuration
of programmable devices and testing of electronic systems, using the IEEE 1149.1
JTAG interface. Jam STAPL is a freely licensed open standard. The Jam Player
provides an interface for manipulating the IEEE Std. 1149.1 JTAG TAP state machine.
For more information about JTAG and Jam STAPL in embedded environments, refer
to
download the jam player, visit the Altera website (www.altera.com).
Configuring Cyclone III Device Family with the JRunner Software Driver
The JRunner software driver allows you to configure Cyclone III device family
through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The supported
programming input file is in .rbf format. The JRunner software driver also requires a
Chain Description File (.cdf) generated by the Quartus II software. The JRunner
software driver is targeted for embedded JTAG configuration. The source code is
developed for the Windows NT operating system (OS). You can customize the code to
make it run on your embedded platform.
The .rbf used by the JRunner software driver cannot be a compressed .rbf because the
JRunner software driver uses JTAG-based configuration. During JTAG-based
configuration, the real-time decompression feature is not available.
For more information about the JRunner software driver, refer to
Software Driver: An Embedded Solution for PLD JTAG Configuration
on the Altera website at (www.altera.com).
Combining JTAG and AS Configuration Schemes
You can combine the AS configuration scheme with the JTAG-based configuration
(Figure
download cable is used in JTAG mode to configure the Cyclone III device family
directly using the JTAG interface. The other download cable is used in AS mode to
program the serial configuration device in-system using the AS programming
interface. The MSEL[3..0] pins must be set to select AS configuration mode
(Table 9–7 on page
simultaneously, the JTAG configuration takes precedence and the AS configuration
terminates.
AN 425: Using Command-Line Jam STAPL Solution for Device
9–29). This setup uses two 10-pin download cable headers on the board. One
9–11). If you try configuring the device using both schemes
Cyclone III Device Handbook, Volume 1
Programming. To
and the source files
AN 414: JRunner
9–57