EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 216

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

9–56
Cyclone III Device Handbook, Volume 1
f
1
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts
the second device to begin configuration. Therefore, if these devices are also in a JTAG
chain, ensure that the nCE pins are connected to GND during JTAG configuration or
that the devices are JTAG configured in the same order as the configuration chain. As
long as the devices are JTAG configured in the same order as the multi-device
configuration chain, the nCEO pin of the previous device drives the nCE pin of the
next device low when it has successfully been JTAG configured. You can place other
Altera devices that have JTAG support in the same JTAG chain for device
programming and configuration.
JTAG configuration allows an unlimited number of Cyclone III device family to be
cascaded in a JTAG chain.
For more information about configuring multiple Altera devices in the same
configuration chain, refer to the
volume 2 of the Configuration Handbook.
Figure 9–28
microprocessor.
Figure 9–28. JTAG Configuration of a Single Device Using a Microprocessor
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
(2) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use a
(3) The nCE pin must be connected to GND or driven low for successful JTAG configuration.
(4) All I/O inputs must maintain a maximum AC voltage of 4.1 V. Signals driving into TDI, TMS, and TCK must fit the
chain.
JTAG configuration, connect the nCONFIG pin to logic high and the MSEL[3..0] pins to ground. In addition, pull
DCLK and DATA[0] either high or low, whichever is convenient on your board.
maximum overshoot equation outlined in
Figure
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
shows JTAG configuration of a Cyclone III device family with a
9–28:
Microprocessor
ADDR
Memory
DATA
Configuring Mixed Altera FPGA Chains
“Configuration and JTAG Pin I/O Requirements” on page
N.C.
(2)
(2)
(2)
Cyclone III Device Family
nCONFIG
DATA[0]
DCLK
TDI
TCK
TMS
nCEO
nCE
(4)
CONF_DONE
(4)
(3)
(4)
MSEL[3..0]
nSTATUS
TDO
V
© December 2009 Altera Corporation
(2)
CCIO
10 kΩ
(1)
V
CCIO
10 kΩ
(1)
Configuration Features
chapter in
9–7.