EP3C25F324I7 Altera, EP3C25F324I7 Datasheet - Page 213

• Manufacturer Part Number: EP3C25F324I7
• Description: IC CYCLONE III FPGA 25K 324 FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25F324I7

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 215
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 324-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 24624
• # I/os (max): 215
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 24624
• Ram Bits: 608256
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• For Use With: 544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Table 9–16. Dedicated Configuration Pin Connections During JTAG Configuration
© December 2009
Signal
nCE
nCEO
MSEL[3..0]
nCONFIG
nSTATUS
CONF_DONE
DCLK
Altera Corporation
On all Cyclone III device family in the chain, nCE must be driven low by connecting it to ground, pulling it
low using a resistor or driving it by some control circuitry. For devices that are also in multi-device AS, AP,
PS, or FPP configuration chains, the nCE pins must be connected to GND during JTAG configuration or
JTAG configured in the same order as the configuration chain.
On all Cyclone III device family in the chain, nCEO is left floating or connected to the nCE of the next
device.
These pins must not be left floating. These pins support whichever non-JTAG configuration that is used in
production. If you only use JTAG configuration, tie these pins to GND.
Driven high by connecting to the V
resistor or driven high by some control circuitry.
Pull to the V
multiple devices in the same JTAG chain, each nSTATUS pin must be pulled up to the V
Pull to the V
multiple devices in the same JTAG chain, each CONF_DONE pin must be pulled up to the V
the bank in which the pin resides individually. CONF_DONE going high at the end of JTAG configuration
indicates successful configuration.
Must not be left floating. Drive low or high, whichever is more convenient on your board.
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an
on-board buffer.
JTAG-chain device programming is ideal when the system contains multiple devices,
or when testing your system using JTAG BST circuitry.
show a multi-device JTAG configuration.
For the device V
maintain a maximum AC voltage of 4.1 V. Because JTAG pins do not have the internal
PCI clamping diodes to prevent voltage overshoot when using V
3.3 V, you must power up the V
V
For device V
the download cable with the supply from V
CCA
.
CCIO
CCIO
supply of the bank in which the pin resides using a 10-kΩ resistor. When configuring
supply of the bank in which the pin resides using a 10-kΩ resistor. When configuring
CCIO
of 1.2, 1.5, and 1.8 V, refer to
CCIO
of 2.5, 3.0, and 3.3 V, refer to
CCIO
supply of the bank in which the pin resides and pulling up using a
CC
of the download cable with a 2.5-V supply from
Description
CCIO
Figure
.
Figure
9–27. You can power up the V
Figure 9–26
9–26. All I/O inputs must
Cyclone III Device Handbook, Volume 1
CCIO
and
of 2.5, 3.0, and
CCIO
Figure 9–27
CCIO
individually.
supply of
CC
9–53
of